HomeComputingMobileInternetGamingElectronicsExtremeDealsExtremeTechComputing14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists…14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists…By Joel Hruska on June 23, 2014 at 10:01 amComment
Share This articleIf you pay any degree of attention to the semiconductor market, the back-and-forth between what is and isn’t possible is liable to give you whiplash. One day we’re talking about silicon hitting a wall at 14nm, and other days we’re talking about pushing towards 5nm and beyond. Reports of profound difficulties and industry delays are interspersed with breathless discussions of new technology, capabilities, and options for continuing to improve semiconductor designs. A new article straddles these two views with a discussion of future CMOS technologies, while simultaneously acknowledging that it’s not clear how many companies will push below the 10nm node.
The complexities of “Will it work?”Ask an economist and an engineer if sub-10nm manufacturing can work and you’re likely to get two completely different answers. These two perspectives often tangle in the comment threads in these types of stories, with some people insisting that we’ll find a way to build better, faster processors, while the more economically-minded focus on the rising cost of transistors and the severe cost pressure this creates.
According to Semiengineering, the industry is evaluating a wide range of technologies for the sub-10nm node including gate-all-around FETs (also called nanowires), quantum well FETs, and silicon-on-insulator FinFETs. Quantum well FETs remain mired in uncertainty while SOI FinFETs continue SOI’s longstanding approach of being the best solution no one ever uses. (Alright, that’s not quite fair. We hear it’s huge in Korea.) That leaves gate-all-around FETs as the most likely approach at 7nm, with germanium as a channel option. This assumes certain difficulties of adapting germanium for the n-channel can be overcome — currently germanium is an excellent p-channel material but more difficult to work with for an n-channel.
III-V semiconductors, which were originally expected to debut at 10nm, are now being pushed back to 7nm or 5nm due to ongoing manufacturing difficulties. EUV remains a consistent challenge, and though manufacturers swear they’ll solve the power problem, the difficulties are staggering. Gate-all-around is an attractive method for improving transistor performance, but manufacturers are still struggling to hit reliability and dimension challenges. Materials like graphene or carbon nanotubes meanwhile, won’t debut for a decade or more in complex CMOS logic devices.
Slow caches can recognize substantial gains over 28nm, but fast cache will scarcely improve over the current generationThis brings us back to the economics question, which is ultimately where the fight will be decided. The question isn’t whether we can continue building to lower process nodes (with the understanding that “node” is merely a label for a group of technologies that deliver an improvement rather than a measure of half-pitch or gate length). The question is whether it makes economic sense to do so. SRAM cells are only getting about 10% smaller per node shrink — they don’t scale very well compared to traditional logic. Other areas (I/O, contact pads) don’t really scale at all.
This creates long-term problems for manufacturers looking to scale designs to smaller nodes, dilutes the value of doing so, and — with costs per node now rising instead of falling — puts increased pressure on design teams. In response, companies like Qualcomm are turning towards different layout methods; the company is now pursuing a monolithic 3D die structure rather than a conventional planar implementation.
This is one area where silicon photonics could play a major role in the future by reducing the power consumption and delay of sending signals over wires, but for now, Qualcomm is planning to work with normal vias and technology. According to the company, a monolithic 3D IC could provide a 30% power savings, 40% performance boost, and cut cost by 5-10% — without changing over to a new node.
The decreasing importance of “nodes”We’re already seeing the end of conventional planar CMOS scaling. TSMC shipped 28nm silicon in 2012, it’ll ship 20nm by the end of 2014 or early 2015 — but the 20nm it ships will be only modestly better than existing 28nm. By the time we see 16nm — which truly improves on 28nm — 2016 will be right around the corner. Sure, companies will keep a two-year cadence for marketing purposes, but the equivalent improvement cycle has pushed out to three years from two. Even Intel has been bitten by the bug — it took the company 27 months to move from 32nm to 22nm and 31-32 months (depending on the launch date) to move from 22nm to 14nm for Broadwell — and that assumes it keeps its current launch target.
Marketing departments at chip companies are going to continue to talk about new nodes because customers are conditioned to expect them. It’s the semiconductor equivalent of Pavlov’s bell, and I don’t expect it will change in the near future. What’s increasingly obvious, however, is that companies are going to start experimenting with new design structures and capabilities in an attempt to defray lithography cost. Qualcomm is talking about monolithic 3D dies, through-silicon vias (TSVs) and other elements of design that cut die space or reduce transistor counts without requiring a node shrink will be increasingly essential.
I’m certain the semiconductor industry will arrive at what it refers to as 7nm and 5nm because that’s what the semiconductor industry does. Whether or not those improvements actually correspond to major lithography changes will be a different story altogether. I suspect that rather than focusing solely on the implementation of new lithgography technology, future nodes will be driven by design improvements — TSMC might declare 7nm to be the node at which it can offer III-V materials and a 3D stacked die with TSVs, rather than just basing the node declaration around physical characteristics.
Tagged In hardwarecomponentsamdcpusARMcpusiliconqualcommsemiconductorscmosmoore's lawCortexgpgpuBroadwellIII-VDennard Scalingscaling7nm5nmShare This Article .article {margin:0px !important;}.AR_1 {margin :0 0 20px 0 !important;}.AR_2 {margin:0 0 20px 0;} CommentPost a Comment Magnus BlombergIf this is true the chip firms should definitely stop putting the length unit “nm” in the node identifiers.
pelov lovIt’s just a marketing term // label at this point.
Magnus BlombergOk then “hands of the length unit!” Call it node generation
massauexcactly tsmc 16nm is just 20nm+ finfet.
intels gate length is also larger than they state.
pelov lovEUV and 450mm wafers were the failed last-ditch efforts — that took decades to develop — to rein in the ever-inflating cost-per-transistor trend that has kicked the entire industry in the groin at sub-28nm nodes. I say were because neither looks like it’s going to make an impact at the 14nm node, and 10nm appears to be unlikely as well. To further make matters worse, the foundries don’t believe there’s enough demand to have the 450mm rollout make financial sense.
To your title, it’s likely the economist that can answer this question. Never mind 5nm and 7nm, but are the diminishing returns are sky-high prices going to severely limit demand for 14nm and 10nm?
Joel HruskaPelov,
I suspect not. 14nm is definitely happening. Industry is full-steam ahead on that one. With EUV now shoving back to sub-10nm, it looks like we’ll be using double-patterning.
pelov lovTriple/Quadruple at the 10nm node and below. Unless I’m mistaken, double-patterning is already happening at 20nm, and 20nm BEOL + FinFETs nodes.
14nm is already done with ramps planned for late this year, so it’s definitely full-steam ahead. But my point is concerning the affordability and not the execution nor timeline. 20nm is already weeding out big players; Qualcomm being pushed to 2015 because Apple has taken all of the wafers for themselves. Come 10nm and even 14nm FinFETs, I don’t think we’ll be seeing the volume we’ve seen with 28nm or will see at 20nm. The prices will certainly be high, but volume is going to be an issue. In fact, that’s exactly why 450mm development has stalled :P
Joel Hruska“14nm is already done with ramps planned for late this year”
This is foundryspeak. I don’t expect a single 14nm design to ship before 2016.
pelov lovI dunno, Joel. When the foundries cheated and stuck with 20nm BEOL, I’ve started to believe they can shorten the leap to FinFETs.
Neutrino .I’m dubious about the extent to which customers are conditioned to expect new nodes to deliver compelling performance gains.
Conventional wisdom is that the slow down in PC sales is mostly down to everyone now doing their work on tablets. Personally I suspect much of the slow down is due to the people that buy PC’s knowing enough about the hardware to recognise that Sandy Bridge didn’t deliver enough over Ivy Bridge to justify an immediate upgrade.
Joel HruskaI’m not saying the lack of new nodes has driven lower sales — I’m saying new nodes are used to signal big improvements.
Sean LumlyWild guess time!
1) I see more and more off-chip facilities being brought onto the SoC and it increasingly being vertically stacked. Though slower, I see a larger push for area-efficient general-purpose logic to swallow some functionality of off-chip fixed function hardware.
2) I guess that while cost scaling has slowed down, it has not stopped, and further R+D may be to reduce costs rather than to deliver smaller features and lower costs together.
3) I also guess that optical interconnects (motivated by speed/power) will become a leading area of research. To add to that, I guess that memory bandwidth will be a subject of increased importance with concern to performance, as it is often the performance limiting factor.
4) I guess that the motherboard will shrink to the point of being tiny; merely useful to hold a few islands of SoCs together and external hardware. PCBs may be replaced with thin-wire optical inter-connects that allow for a flexible layout (not necessarily planar, but 3D).
Joel HruskaSean,
Cost scaling has stopped. Look at the first graph in the story. We’ve been talking about this for two years, 20nm will be more expensive per sq. mm than 28nm. 14/16 is even worse.
You can already buy tiny motherboards, but the primary purpose of the mobo is to provide additional connectivity, RAM slots, and PCI-E expansion capability. There will always be some systems that require such functionality, so we’ll always see the ability baked in at some level.
Sean LumlyPerhaps I mis-communicated what I was trying to say. I was trying to imply that the cost of writing chip features at 20nm (for example) will likely decrease in time (why wouldn’t it?), and by implication am speculating that research will emphasize bringing the cost down alone vs. the node length and cost together. If this is true, then cost-scaling (of a single node over time) has slowed and not stopped. Put a slightly different way, the economic incentive to use sub-28nm chips will not correlate directly with a node-shrink, but will be there when the costs of producing the node decrease to a point that there is sufficient demand.
To imply differently would be quite the prophecy: that producing a 20nm chip today is the cheapest that it will ever be. I do not think that this is a sane prediction.
Tiny motherboards is beside the point. Fewer chips fused to a PCB, and fewer wires (eg. optical interconnect) will continue to reduce MB size and complexity. This is my prediction. The extreme case in this prediction (however out-there) is that a computer will be a chip or two, and not a collection of chips connected via a motherboard.
pelov lov“I was trying to imply that the cost of writing chip features at 20nm (for example) will likely decrease in time (why wouldn’t it?)”
Developing masks for FinFETs nodes is very expensive and time consuming. It’s also even more complicated and involves further steps for SoCs and other chips that have many separate blocks operating at different voltages and frequencies.
Sean LumlySure. But are you implying that the cost of doing this will never drop?
pelov lovThey undoubtedly will, but that cost has nothing to do with $-paid-per-wafer, the much bigger cost, which won’t drop by any significant amount.
Fabs for 20nm and under cost upwards of $10bn. I can’t find the article right now, but wafers cost 20-30% more than 28nm did at introduction (might be even higher), and those costs aren’t going to decrease. FinFETs increases cost by a smaller margin, but complexity increases significantly.
Cost-per-transistor has stopped scaling according to Moore’s law at 28nm, and it gets exponentially more expensive the smaller you go. This doesn’t just apply to the foundries, but to their customers and their respect WSAs as well.
Sean LumlyI’m not sure what you think I’m arguing, but I’m not arguing that smaller nodes are currently more expensive to produce — this has been well established.
pelov lovThis is the gist of it, correct?
“Perhaps I mis-communicated what I was trying to say. I was trying to imply that the cost of writing chip features at 20nm (for example) will likely decrease in time (why wouldn’t it?), and by implication am speculating that research will emphasize bringing the cost down alone vs. the node lengthand cost together”
And it’s true, but that amount saved is very small when you take into account the entirety of all of the costs involved. Complexity of design and implementation (writing chip features?) has gone up tremendously and it’s decreasing less for newer nodes — say 20nm or FinFETs — than it did for 28nm and up.
Sean LumlyThat the cost (eg. of a chip with 20nm features) will drop by a “very small” amount is entirely speculative and implies that something is known about future technologies. I seriously doubt this prediction, and expect them to drop drastically given time and science.
pelov lovI don’t doubt they’ll drop, but only if you’re looking at this 5+ years down the road and alternative approaches that aren’t even on the horizon yet. Most engineers and statements from fabs and their customers have stated that they expect cost and complexity to increase exponentially and not decrease, but more importantly that the saviors — EUV and 450mm — are nowhere in sight. This isn’t speculation and rumor, but statements from the same companies developing that technology. This is why you hear 28nm is a “long life node.” Anything below that is on the wrong end of the $-per-transistor curve.
When people say Moore’s law is dead, they mean dead as in dead.
Sean LumlyThen you, in fact, agree rather than disagree: cost hasn’t stopped descending.
pelov lovIt has, and that’s why Moore’s law is dead and foundries and customers alike have said so. What I agree with you on is that the cost of a *specific node and/or process* decreases over time, but that decrease in cost is very tiny percentage of overall cost, which is increasing exponentially. In fact, it’s so tiny that 28nm is going to look better for a lot of customers for a very long time.
Sean LumlyNow you’re directly contradicting yourself.
pelov lovUhhh… no, I’m not.
Volume, cost-per-wafer, yield, and other factors can increase the cost (WSAs can vary as well) of a specific node and/or process early on in its lifetime yet they subside somewhat as the kinks are worked out. That decrease is smaller than it used to be, though. That also doesn’t make the following node and/or process any less expensive. In fact, they’re still exponentially more expensive.
A great example is what we’re seeing at TSMC today, where Apple has had to pay TSMC a pretty penny — higher than what could be considered “standard” — in order to chew up nearly all of TSMC’s early 20nm capacity. Consequently, Qualcomm, MediaTek, nVidia, AMD, and others have all had to bump release dates of 20nm silicon to 1H 2015 while Apple will probably see a release this year.
Sean LumlyThree posts up you said that you don’t doubt that costs will decline (you gave the example of +5 years out). Then you directly disagreed with the statement that costs haven’t stopped declining.
pelov lovI don’t doubt it, but you’re looking at future technologies that aren’t even on the roadmap yet — III-V, photonics on-chip, graphene, etc. For the short term, and we’re talking 5-10 years as a “short term”, costs are going to increase exponentially.
Qualcomm isn’t looking at 3D monolithic dies, an incredibly complex and costly endeavor, because prices for wafers are decreasing or because $$-per-transistor is getting better. That doesn’t make any bit of sense.
Joel Hruskahttp://www.extremetech.com/wp-content/uploads/2012/03/NV-Pres3.jpg
Here’s some context from an NV presentation back in 2012. This graph remains true.
Look at the normalized transistor cost curve for each node. It shows that yes, initially, costs are extremely high, but the long-term normalized cost eventually delivers a marked improvement…except that stops.
It takes 11 quarters and 8 quarters (estimated) for 20nm and 14nm to *reach* parity with 28nm costs — and NV doesn’t think they ever go lower.
http://www.extremetech.com/wp-content/uploads/2013/07/LithoCost.jpg
There’s the impact of lithography on total wafer costs. Note that the last two data points assume EUV was available — except EUV *isn’t* available, which means the costs *aren’t* going to come back down. With lithography now accounting for more than 50% of total manufacturing cost, the opportunity for other backend optimizations to improve cost structures is small and getting smaller. By 10nm or below, lithography will account for 70% or more of cost.
massaumaybe the question is which version of moores law is dead.
i know 3 version:
V1:the transistors per chip double every X time.
V2:the cost of the transistors will halve every X time.
V3:the size of a transistor will halve every X time.
the first 2 can still be done if they can create a way to do cheap 3D stacking and lower the costs of current nodes.
also if they really want to find a way to reduce costs than they should find an other way than the EUV. the best would be a maskless lithography. but it is still far away and everyone has bet on EUV.
pelov lovMoore’s law, as it was intended, refers to the anomaly that the number of transistors doubles every two years for a fixed cost – cost per wafer, for instance.
The cost factor is important, because if you don’t maintain a certain cost then it makes no financial sense. Why would a foundry invest in a new node/process if there’s no money to be made? Why would a customer jump to the following node if there is no cost advantage?
The various interpretations of Moore’s law that float about tend to forget that foundries cost upwards of tens of billions of dollars. There’s no way Moore’s law would exist if there wasn’t a financial inventive to pursue it in the first place :)
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